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Micrel, Inc.
2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE
SuperLiteTM SY55856U SuperLiteTM
SY55856U
FEATURES
s Guaranteed AC parameters over temp and voltage * > 2.5GHz fMAX * < 384ps prop delay * < 120ps tr/tf s Delay either clock or data s 50ps increments s 350ps total delay s Source terminated CML outputs s Full differential I/O s Wide supply voltage spectrum: 2.3V to 3.6V s Available in a tiny 32-pin EPAD-TQFP package SuperLiteTM
DESCRIPTION
The SY55856U is a 2.5GHz, two-channel, fully differential CML (Current Mode Logic) delay line. The device is optimized to adjust the relative delay between two channels, such as clock and data, in 50ps increments. Both inputs may be adjusted in either direction in 7 increments of 50ps, for a total adjustment range of 350ps. In addition, the clock input maybe inverted through the CINV control pin. The SY55856U inputs are designed to accept singleended or differential CML signals. The differential CML outputs are optimized for 50 loads (50 source terminated), thus only requires a single 100 resistor across the output pair. Output rise and fall time is an extremely fast 110ps(max) and the differential swing is 400mV. The maximum throughput of the SY55856U is guaranteed to exceed 2.5GHz (5Gbps).
APPLICATIONS
s s s s s s Data communications systems Telecom systems High-speed backplanes Signal de-skewing Pulse alignment Digitally controlled delay lines
SuperLite is a trademarks of Micrel, Inc. M9999-011207 hbwhelp@micrel.com or (408) 955-1690
Rev.: E Amendment: /0
1
Issue Date: January 2007
Micrel, Inc.
SuperLiteTM SY55856U
PACKAGE/ORDERING INFORMATION
DELAY_SEL
Ordering Information(1)
VCC VCC
VCC
VCC
Part Number
/DATA_OUT GND DATA_OUT GND GND CLK_OUT GND /CLK_OUT
Package Type H32-1 H32-1 H32-1 H32-1
Operating Range Industrial Industrial Industrial Industrial
Package Marking 55856U 55856U
Lead Finish Sn-Pb Sn-Pb
S2
S1
32 31 30 29 28 27 26 25 /DATA_IN GND DATA_IN GND GND CLK_IN GND /CLK_IN 1 2 3 4 5 6 7 8 9 VCC 10 11 12 13 14 15 16 CINV VCC NC NC VCC VCC LVL 24 23 22
S0
SY55856UHI SY55856UHITR(2) SY55856UHG(3) SY55856UHGTR(2, 3)
Top View EPAD-TQFP H32-1
21 20 19 18 17
55856U with NiPdAu Pb-Free bar line indicator Pb-Free 55856U with NiPdAu Pb-Free bar line indicator Pb-Free
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
32-Pin EPAD-TQFP (H32-1)
PIN DESCRIPTION
Pin Number 1, 3 2, 4, 5, 7, 18, 20. 21, 23 22, 24 6, 8 17, 19 9, 10, 15, 16 25, 26, 31, 32 11 Pin Name /DATA_IN, DATA_IN GND DATA_OUT, /DATA_OUT CLK_IN, /CLK_IN /CLK_OUT, CLK_OUT VCC CINV Pin Function CML Input (Differential). This is one of the CML inputs, the data in signal. A delayed version of this signal appears at DATA_OUT, /DATA_OUT. Ground. CML Output (Differential). This is one of the CML outputs, the data output. It is a delayed version of DATA_IN , /DATA_IN. CML Input (Differential). This is one of the differential CML inputs, the clock in signal. A delayed version of this input appears at CLK_OUT, /CLK_OUT. CML Output (Differential). This is one of the CML outputs, the clock output. It is a delayed, copy of CLK_IN, /CLK_IN. Power Supply. VT Input (Single Ended). This is the clock inversion select signal. This input optionally inverts the CLK_IN, /CLK_IN signal which results in an inverted CLK_OUT, /CLK_OUT. A voltage below the VT threshold results in no inversion. A voltage above the threshold value results in an inversion from the clock input to the clock output. Refer to the "VT input" section below. Analog Input. This input determines what level differentiates logic high from logic low. This input affects the behavior of the CINV, S0, S1 and S2 inputs. Please refer to the "VT input" section below for more details. For the control interface, see Figure 3a. For TTL control interface, see Figure 3b. VT Input (Single Ended). CML compatible control logic. This is the delay path control input. Logic high delays the clock signal with respect to the data signal. A logic low delays the data signal with respect to the clock signal. Inputs S2, S1 and S0 control amount of delay. VT Input (Single Ended). CML compatible control logic. This is the delay selection control input. These three bits define how much relative delay will occur between the data and clock signals, as per the truth table shown in Table 2. For the control logic interface, see Figure 3a. For TTL control interface, see Figure 3b. S0=LSB. No Connect.
14
LVL
30
DELAY_SEL
27, 28, 29
S0, S1, S2
12, 13
NC
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Micrel, Inc.
SuperLiteTM SY55856U
BLOCK DIAGRAM
VCC DATA_IN /DATA_IN
A0 A1 A3 A2 A4 A5 A6 INPUT BUFFER A7 S1 S0 S2
DATA_OUT /DATA_OUT
S2
S1 5k LVL 5k VREF = 1.3V A0 A1 A3 A2 A4 A5 A6 CLK_IN /CLK_IN INPUT BUFFER A7 S1 S2 S0 S0 DEL_SEL
CLK_OUT /CLK_OUT
CINV GND
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Micrel, Inc.
SuperLiteTM SY55856U
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs The true pin of a CML input pair is internally biased to ground through a 75k resistor. The complement pin of a CML input pair is internally biased halfway between VCC and ground by a voltage divider consisting of two 75k resistors. To keep a CML input at static logic zero at VCC > 3.0V, leave both inputs unconnected. For VCC 3.0V, connect the complement input to VCC and leave the true input unconnected. To make an input static logic one, connect the true input to VCC, and leave the complement input unconnected. These are the only safe ways to cause CML inputs to be at a static value. In particular, no CML input should be directly connected to ground. All NC pins in the figures below should be left unconnected. VT (Variable Threshold) Inputs Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and S2, are variable threshold inputs. The LVL input determines the Voltage threshold that differentiates logic high from logic low for these five inputs only. If LVL is left unconnected, the or V TCL, 2 whichever is higher. To obtain a logic switching threshold different from this, the LVL input must be driven with the actual desired threshold voltage. The user may drive the LVL pin with any voltage between VCC - 0.1V and ground. For example, driving LVL with a voltage set at Vcc - 1.3V causes the VT inputs to accept single ended PECL outputs and switch appropriately. Note that VT inputs are internally clamped so that the threshold will not fall below VTCL Volts. Since driving the LVL input to ground causes the threshold to be somewhere between VTCL (min) and VTCL (max), it is expected that the user will keep the Voltage at the LVL pin at or above VTCL (max). Please refer to Figure 3 for clarification. VT inputs will switch at about
VCC + GND
NC
IN /IN
VCC NC
IN /IN
NC
VCC > 3.0V
Figure 1. Hard Wiring a Logic "1"(1)
NC VCC
IN /IN
Logic Switching Threshold VCC VCC -- 0.1V
VCC 3.0V
Figure 2. Hard Wiring a Logic "0"(1)
VCC VTCL Operating Range VTCL VCC -- 0.1V VCC LVL Input TTL Driver
3.0V VCC 3.6V 1.10k 3
VCC
SY55856 S0, S1, S2 LVL
909
Figure 3a. Logic Switching Threshold
Note 1. IN is either the DATA_IN or the CLK_IN input. /IN is either the / DATA_IN or the /CLK_IN input.
Figure 3b. Interfacing TTL-to-CML Select (CINV, DELAY_SEL, S0, S1, S2)
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Micrel, Inc.
SuperLiteTM SY55856U
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VIN VOUT TA TLEAD Tstore JA Power Supply Voltage Input Voltage CML Output Voltage Operating Temperature Range LeadcTemperature (soldering, 20sec.) Storage Temperature Range Package Thermal Resistance (Junction-to-Ambient) Exposed pad soldered to PCB GND pin Package Thermal Resistance (Junction-to-Case) - Still Air - 500lfpm Rating Value -0.5 to +6.0 -0.5 to VCC+5.0 -0.5 to VCC+5.0 -40 to +85 260 -55 to +125 28 20 Unit V V V C C C C/W C/W
JC
Note 1.
4
C/W
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability.
CML TERMINATION
All CML inputs accept a CML output from any other member of this family. All CML outputs are source terminated 50 differential drivers as shown in Figure 4. SY55856U expects its inputs to be externally terminated. SY55856U inputs are designed to accept a termination resistor between the true and complement inputs of a CML differential input pair, as shown in Figure 4.
VCC
50
50
50 100 50
16mA
SY55856U
Figure 4. 50 Load CML Output
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SuperLiteTM SY55856U
TRUTH TABLES
DATA_IN CLK_IN CINV 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
DATA_OUT /DATA_OUT CLK_OUT /CLK_OUT 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1
Table 1. Input to Output Connectivity
S2 0 0 0 0 1 1 1 1
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
DATA_OUT (D_SEL=0) (ps) 350 300 250 200 150 100 50 0
CLK_OUT (D_SEL=1) (ps) 0 50 100 150 200 250 300 350
Table 2. Nominal Differential Delay Values
Note: 1. Table 2 defines the approximate relative delay between the two paths. For example, if S2, S1, S0 = 000, and an edge appears at CLK_IN at the same instant as an edge appears at DATA_IN, then an edge at CLK_OUT will appear about 350ps earlier than an edge at DATA_OUT. That is, negative values imply CLK_OUT being shifted early with respect to DATA_OUT. Likewise, a positive value in the third column implies that CLK_OUT is shifted late with respect to DATA_OUT. Please consult the "AC ELECTRICAL CHARACTERISTICS" section for more precise delay values.
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Micrel, Inc.
SuperLiteTM SY55856U
DC ELECTRICAL CHARACTERISTICS
TA = -40C Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 2.3 -- Typ. -- -- Max. 3.6 140 Min. 2.3 -- TA = +25C Typ. -- 115 Max. 3.6 140 Min. 2.3 -- TA = +85C Typ. -- -- Max. 3.6 140 Unit V mA No Load Condition
VT INPUTS DC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V; TA = -40C to +85C(1) Symbol VILVL VIHVT VILVT VIST VTCL
Note 1. Note 2.
Parameter Analog Input(2) Voltage(3,4) Voltage(3,4)
Min. VTCL VSW + 0.1 0.0 100 1.2
Typ. -- -- -- 50 --
Max. VCC - 0.1 VCC VSW - 0.1 -- 1.4
Unit V V V mV V
VT Input High VT Input High
Input Switching Threshold Differential Voltage(5) Threshold Clamp Voltage
DC parameters are guaranteed after thermal equilibrium has been established. The LVL input determines the voltage switching threshold that differentiates logic high from logic low for the VT inputs S0, S1, S2, DELAY_SEL, and CINV. LVL may be driven to VCC, but this is not useful, as the VT inputs could then not get high enough to reliably indicate logic high. Also, as shown in Figure 3, the LVL input internally clamps at VTCL. If LVL is left unconnected, the VT inputs will switch at about the maximum of VCC + GND VCC and VTCL. = 2 2
Note 3. Note 4. Note 5.
VT inputs are S0, S1, S2, DELAY_SEL, and CINV. VSW is the threshold switching voltage. It is equal to the voltage at the LVL pin, when this voltage is above VTCL (max). VSW is some value between VTCL (min) and VTCL (max) when the Voltage at the LVL pin is below VTCL (max). VIST is the voltage difference needed to guarantee a stable logic level. Logic high must be at least VIST above VSW. Logic low must be at most VIST below VSW. Thus, the minimum input swing on a given VT input pin, that is, |VIHVT - VILVT|, must be at least 2xVIST.
CML DC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V; TA = -40C to +85C Symbol VID VIH VIL VOH VOL VOUT (Swing) ROUT Parameter Differential Input Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Voltage Swing(6) Min. 100 1.6 1.5 VCC -0.040 VCC -1.00 0.650 -- 40 Typ. -- -- -- VCC -0.010 VCC -0.800 0.800 0.400 50 Max. -- VCC VCC -0.1 VCC VCC -0.65 1.00 -- 60 Unit mV V V V V V No Load No Load No Load
50 Environment
Condition
Output Source Impedance (CLK_OUT, /CLK_OUT and DATA_OUT, /DATA_OUT)
Note 6.
VOUT(SWING) is defined as the swing on one output of a differential pair, that is |VOH - VOL| on one pin. The swing for common mode noise immunity purposes is 2 x VOUT(SWING). Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in a 50 environment. Refer to "CML Termination" figures for more details.
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Micrel, Inc.
SuperLiteTM SY55856U
AC ELECTRICAL CHARACTERISTICS(7)
VCC = 2.3V to 3.6V; GND = 0V TA = -40C Symbol fMAX t tPLH tPHL tDELAY tJITTER tSKEW DC tr/tf
Note 7. Note 8.
TA = +25C Min. 2.5 36 232 290 -- -- 45 -- Max. -- 52 384 420 <1 50 55 110
TA = +85C Min. 2.5 36 232 335 -- -- 45 -- Max. -- 52 384 465 <1 50 55 120 Unit GHz ps ps ps psRMS ps % ps
Parameter Maximum Frequency Delay step size Delay line insertion delay(8) Delay line range Output jitter Delay line duty cycle skew (ItPLH-tPHLI) Duty cycle CML Output rise/fall time (20% to 80%)
Min. 2.5 36 232 250 -- -- 45 --
Max. -- 52 384 365 <1 50 55 100
Tested using the 50W load, as shown in Figure 4. Delay line insertion delay is the minimum input-to-output delay with select control set to S2:S0 = 0 for CLK_OUT and S2:S0 = 7 for DATA_OUT. This resulting delay is the inherent propagation delay.
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Micrel, Inc.
SuperLiteTM SY55856U
32-PIN EPAD-TQFP (DIE UP) (H32-1)
Rev. 01
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FAX
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The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-011207 hbwhelp@micrel.com or (408) 955-1690
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